Terminal structure with depression region below dielectric wall and semiconductor package having the same

A semiconductor package, comprising:

• an interconnect substrate, configured with depression regions along a periphery thereof and including a plurality of electrically conductive elements, a crack-inhibiting dielectric frame and an interfacial dielectric layer;
• a semiconductor device, attached to the interconnect substrate and electrically connected to the electrically conductive elements;
• and
• a sealant, encapsulating the semiconductor device, wherein:
• each of the depression regions has an open lateral end at the periphery of the interconnect substrate, a closed lateral end opposite to the open lateral end, and a depression surface at a level between top and bottom surfaces of the electrically conductive elements;
• the electrically conductive elements are disposed within compartments defined by the crack-inhibiting dielectric frame and spaced from each other by the interfacial dielectric layer and each has an outward lateral surface as the closed lateral end of the depression region and adjacent to the depression surface of the depression region;
• the crack-inhibiting dielectric frame is superimposed over the depression regions and has inner lateral edges coated by the interfacial dielectric layer;
• and
• the interfacial dielectric layer laterally covers and surrounds the electrically conductive elements and has inner lateral surfaces that form, collectively with the outward lateral surfaces of the electrically conductive elements, boundaries of the depression regions.