US 2026/0136610 A1 · Power Semiconductor Packaging and Manufacturing Method Thereof

Abstract

The power semiconductor device comprises a substrate with a first epitaxial layer disposed above the substrate. The first epitaxial layer comprises a first doped channel located in a peripheral area surrounding a unit area, and the first doped channel extends vertically across the first epitaxial layer. A second epitaxial layer, disposed on the first epitaxial layer, comprises a second doped channel located in the peripheral area and above the first doped channel. The second doped channel extends vertically across the second epitaxial layer. A junction layer is disposed above the second doped channel, with a first electrode located on the junction layer. Current flows from the substrate through the first and second doped channels, the junction layer, and to the first electrode.

Claims20

Dependent claims

A power semiconductor device, comprising:

a substrate;
a first epitaxial layer disposed above the substrate, wherein the first epitaxial layer comprises a first doped channel located in a peripheral area surrounding a unit area, and wherein the first doped channel extends vertically across the first epitaxial layer;
a second epitaxial layer disposed on the first epitaxial layer, wherein the second epitaxial layer comprises a second doped channel located in the peripheral area and above the first doped channel, and wherein the second doped channel extends vertically across the second epitaxial layer;
a junction layer disposed above the second doped channel;
a first electrode located on the junction layer;
wherein current flows from the substrate through the first and second doped channels, the junction layer, and to the first electrode.

3 more elements

Dependencies are inferred from the claim text.

Power Semiconductor Packaging and Manufacturing Method Thereof

Life of this patent

Power Semiconductor Packaging and Manufacturing Method Thereof

Life of this patent

Abstract

Claims20