Double poly non-volatile memory bit cell

An integrated circuit, comprising:

• a logic block;
• and
• a non-volatile memory (NVM) bit-cell array coupled to the logic block, the NVM bit-cell array comprising a plurality of NVM bit cells arranged in multiple rows and in multiple columns, each NVM bit cell comprising:
• a control gate comprising:
• floating terminal formed by a first polysilicon layer;
• a control terminal formed by a second polysilicon layer;
• and
• a control-gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control-gate dielectric layer includes a high-K dielectric layer;
• a state transistor comprising:
• a floating-gate terminal formed by the first polysilicon layer and coupled to the floating terminal of the control gate;
• and
• a tunnel oxide layer formed between the first polysilicon layer and an active area of the state transistor;
• and
• an access transistor coupled in series with the state transistor.

A method, comprising:

• forming a well region;
• forming an access transistor in the well region;
• forming a state transistor in the well region, the state transistor having a floating-gate terminal formed by a first polysilicon layer;
• forming a control gate having a floating terminal formed by the first polysilicon layer, a control terminal formed by a second polysilicon layer, and a control-gate dielectric layer disposed between the first and second polysilicon layers and including a high-K dielectric layer.