Hybrid top-bottom plate sampling scheme in successive approximation register (sar) analog-to-digital converter (adc) for charge injection reduction

An analog-to-digital converter (ADC), comprising:

• a comparator;
• a first sampling switch coupled to a first input of the comparator;
• a capacitive digital-to-analog convert (DAC), the capacitive DAC comprising:
• a first capacitor array comprising first capacitors, wherein top plates of the first capacitors are coupled between the first sampling switch and the first input of the comparator;
• and
• a first switching circuit configured to selectively couple bottom plates of the first capacitors to a common mode voltage;
• a switch control circuit configured to:
• during a first phase, close the first sampling switch and cause the first switching circuit to couple the bottom plates of the first capacitors to the common mode voltage;
• during a second phase, cause the first switching circuit to decouple the bottom plates of the first capacitors from the common mode voltage while the first sampling switch is closed;
• during a third phase, open the first sampling switch while the bottom plates of the first capacitors are decoupled from the common mode voltage;
• and
• during a fourth phase, cause the first switching circuit to couple the bottom plates of first capacitors to the common mode voltage while the first sampling switch is open;
• and
• a successive approximation register (SAR) coupled to an output of the comparator, wherein, during the fourth phase, the SAR is configured to make a bit decision based on the output of the comparator.