Stress-tolerant semiconductor device and level shifter

An apparatus having a stress-tolerant semiconductor device comprising:

• a source terminal, a gate terminal, a gate-control terminal, and a drain terminal;
• a first transistor having a source connected to the source terminal of the stress-tolerant semiconductor device, a gate connected to the gate terminal of the stress-tolerant semiconductor device, and a drain;
• a second transistor having a source connected to the drain of the first transistor, a gate connected to the gate-control terminal of the stress-tolerant semiconductor device, and a drain;
• a third transistor having a source connected to the drain of the second transistor, a drain connected to the drain terminal of the stress-tolerant semiconductor device, and a gate;
• a fourth transistor having a drain connected to the gate-control terminal of the stress-tolerant semiconductor device, a gate connected to the drain terminal of the stress-tolerant semiconductor device, and a source;
• and
• a fifth transistor comprising a source connected to the source of the fourth transistor, a gate connected to the gate-control terminal of the stress-tolerant semiconductor device, and a drain connected to the drain terminal of the stress-tolerant semiconductor device;
• wherein a conductivity type of said first, second and third transistors is opposite to a conductivity type of said fourth and fifth transistors.