Comparison circuit performing comparator offset calibration and method of operating the same

A method of operating a comparison circuit including at least one transistor, the method comprising:

• determining whether an operation mode of the comparison circuit is an offset calibration mode or a normal mode;
• when the operation mode of the comparison circuit is the offset calibration mode, performing an offset calibration operation by degrading the at least one transistor based on first and second input signals having the same voltage level and an operating clock signal;
• and
• when the operation mode of the comparison circuit is the normal mode, performing a normal operation based on the first and second input signals having different voltage levels and the operating clock signal.

A comparison circuit comprising:

• a comparator including at least one transistor and configured to generate a first output signal based on a first input signal, a second input signal, and an operating clock signal;
• and
• a multiplexer configured to:
• in a normal mode, output a first clock signal as the operating clock signal based on a control signal, and
• in an offset calibration mode, output a second clock signal different from the first clock signal as the operating clock signal based on the control signal,
• wherein, in the offset calibration mode, the first input signal and the second input signal have the same voltage level,
• wherein the comparator includes:
• a first p-channel metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor connected in parallel between a terminal to which a power supply voltage is applied and a terminal from which the first output signal is output, the first PMOS transistor including a gate terminal connected to a terminal to which the operating clock signal is input, the second PMOS transistor including a gate terminal connected to a terminal from which a second output signal is output;
• a third PMOS transistor and a fourth PMOS transistor connected in parallel between the terminal to which the power supply voltage is applied and the terminal from which the second output signal is output, the third PMOS transistor including a gate terminal connected to the terminal from which the first output signal is output, the fourth PMOS transistor including a gate terminal connected to the terminal to which the operating clock signal is input;
• a first n-channel metal-oxide semiconductor (NMOS) transistor and a second NMOS transistor connected in series between the terminal from which the second output signal is output and a first node, the first NMOS transistor including a gate terminal connected to the terminal from which the first output signal is output, the second NMOS transistor including a gate terminal connected to a terminal to which the first input signal is input;
• a third NMOS transistor and a fourth NMOS transistor connected in series between the terminal from which the first output signal is output and the first node, the third NMOS transistor including a gate terminal connected to the terminal from which the second output signal is output, the fourth NMOS transistor including a gate terminal connected to a terminal to which the second input signal is input;
• and
• a fifth NMOS transistor connected between the first node and a ground node, and including a gate terminal connected to the terminal to which the operating clock signal is input,
• wherein, in the offset calibration mode, when a voltage level of the gate terminal of the second NMOS transistor is higher than a voltage level of the gate terminal of the fourth NMOS transistor, the comparison circuit is configured such that the second PMOS transistor has a threshold voltage being decreased, and
• wherein the comparison circuit is configured to:
• perform the offset calibration operation in the offset calibration mode during a manufacturing process of the comparison circuit, and
• perform a normal operation in the normal mode after the manufacturing process of the comparison circuit.