Floating inverter amplifier based on capacitor stacking and application thereof

A floating inverter amplifier based on capacitor stacking, comprising a differential-structured inverter and a capacitor charge-discharge array, wherein the capacitor charge-discharge array supplies power to the inverter by means of two capacitors that are reset first and then stacked end-to-end:

• wherein the inverter comprises two PMOS transistors M1 and M2, two NMOS transistors M3 and M4, and two switches S8 and S9, wherein a source of M1 and a source of M2 are connected together and to a floating power rail of the capacitor charge-discharge array, a source of M3 and a source of M4 are connected together and to a floating ground rail of the capacitor charge-discharge array, a drain of M1 and a drain of M3 and one end of S8 are connected together as an inverting output terminal of the inverter, a drain of M2 and a drain of M4 and one end of S9 are connected together as a non-inverting output terminal of the inverter, a gate of M1 and a gate of M3 are connected together as a non-inverting input terminal of the inverter, a gate of M2 and a gate of M4 are connected together as an inverting input terminal of the inverter, the other end of S8 and the other end of S9 are connected together and to a power supply voltage VDD, and on/off of the switches S8 and S9 are controlled by a clock signal φ1;
• wherein, as an alternative embodiment, the inverter is based on a cascode structure, comprising six PMOS transistors M1, M2, M5, M6, M7, and M8, six NMOS transistors M3, M4, M9, M10, M11, and M12, and two switches S8 and S9, wherein a source of M1 and a source of M2 are connected together and to a floating power rail of the capacitor charge-discharge array, a drain of M1 is connected to a source of M5 and a source of M6, a drain of M2 is connected to a source of M7 and a source of M8, a source of M3 and a source of M4 are connected together and to a floating around rail of the capacitor charge-discharge array, a drain of M3 is connected to a source of M9 and a source of M10, a drain of M4 is connected to a source of M11 and a source of M12, a drain of M5 and a drain of M6, a drain of M9, a drain of M10, and one end of S8 are connected together as an inverting output terminal of the inverter, a drain of M7 and a drain of M8, a drain of M11, a drain of M12, and one end of S9 are connected together as a non-inverting output terminal of the inverter, a gate of M1, a gate of M3, a gate of M5, a gate of M8, a gate of M9, and a gate of M12 are connected together as a non-inverting input terminal of the inverter, a gate of M2, a gate of M4, a gate of M6, a gate of M7, a gate of M10, and a gate of M11 are connected together as an inverting input terminal of the inverter, the other end of S8 and the other end of S9 are connected together and to the power supply voltage VDD, and on/off of the switches S8 and S9 are controlled by a clock signal φ1;
• wherein the capacitor charge-discharge array comprises seven switches S1 to S7 and two capacitors CRES1 and CRES2, wherein one end of S1 is connected to the power supply voltage VDD, the other end of S1 is connected to one end of CRES1 and one end of S6, one end of S2 is connected to the power supply voltage VDD, the other end of S2 is connected to one end of CRES2 and one end of S5, the other end of S5 serves as the floating power rail of the capacitor charge-discharge array, the other end of S6 is connected to the other end of CRES2 and one end of S4, the other end of S4 is grounded, the other end of CRES1 is connected to one end of S3 and one end of S7, the other end of S3 is grounded, the other end of S7 serves as the floating around rail of the capacitor charge-discharge array, the on/off of the switches S1 to S4 are controlled by the clock signal φ1, and the on/off of switches S5 to S7 are controlled by the clock signal φ2.