Voltage generation circuit, memory device, and memory system

A memory device, comprising:

• a memory cell array;
• and
• a peripheral circuit coupled to the memory cell array, the peripheral circuit comprises one or more voltage generation circuits, each of the voltage generation circuits comprising:
• a clock voltage doubling circuit comprising a first signal generation circuit, a second signal generation circuit and a first output circuit;
• and
• a charge pump circuit, wherein:
• the first signal generation circuit is connected with a first electrode and a second electrode of a metal oxide semiconductor (MOS) transistor in the first output circuit, the second signal generation circuit is connected with a third electrode of the MOS transistor in the first output circuit, and the second electrode of the MOS transistor in the first output circuit is connected with the charge pump circuit;
• the first signal generation circuit is configured to apply a positive voltage signal to the first electrode of the MOS transistor in the first output circuit and apply a source voltage signal to the second electrode of the MOS transistor in the first output circuit under control of an input first clock signal;
• the second signal generation circuit is configured to apply a second clock signal different from the input first clock signal to the third electrode of the MOS transistor in the first output circuit under the control of the input first clock signal;
• and
• the first output circuit is configured to output a voltage doubling clock signal to the charge pump circuit under control of the second clock signal.

A memory system, comprising:

• one or more memory devices;
• and
• a controller coupled to the memory devices and configured to control the memory devices, wherein:
• each of the memory devices comprises:
• a memory cell array;
• and
• a peripheral circuit comprising one or more voltage generation circuits, each of the voltage generation circuits comprising:
• a clock voltage doubling circuit comprising a first signal generation circuit, a second signal generation circuit and a first output circuit;
• and
• a charge pump circuit, wherein:
• the first signal generation circuit is connected with a first electrode and a second electrode of a metal oxide semiconductor (MOS) transistor in the first output circuit, the second signal generation circuit is connected with a third electrode of the MOS transistor in the first output circuit, and the second electrode of the MOS transistor in the first output circuit is connected with the charge pump circuit;
• the first signal generation circuit is configured to apply a positive voltage signal to the first electrode of the MOS transistor in the first output circuit and apply a source voltage signal to the second electrode of the MOS transistor in the first output circuit under the control of an input first clock signal;
• the second signal generation circuit is configured to apply a second clock signal different from the input first clock signal to the third electrode of the MOS transistor in the first output circuit under the control of the input first clock signal;
• and
• the first output circuit is configured to output a voltage doubling clock signal to the charge pump circuit under the control of the second clock signal.