Greater than Binary State Digital Logic for Superconductive Circuits
AssigneeMassachusetts Institute of Technology
InventorsMatthew GUYTON, Alexander WYNN, Chad MEINERS
Life of this patent
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Abstract
In some embodiments, a multistate memory cell includes; a storage loop comprising one or more superconducting devices and one or more inductive devices, the storage loop configured to maintain a quantized magnetic field representing a stored state of the multistate memory cell, the stored state from among a set of three or more distinct digital states; and at least three address lines each inductively coupled to the storage loop, wherein, in response to currents applied to the at least three address lines, the inductive couplings of the at least three address lines combine to force the quantized magnetic field to represent a particular one of the three or more distinct digital states.
Claims19
A multistate memory cell comprising:
- a storage loop comprising one or more superconducting devices and one or more inductive devices, the storage loop configured to maintain a quantized magnetic field representing a stored state of the multistate memory cell, the stored state from among a set of three or more distinct digital states;
- and
- at least three address lines each inductively coupled to the storage loop, wherein, in response to currents applied to the at least three address lines, the inductive couplings of the at least three address lines combine to force the quantized magnetic field to represent a particular one of the three or more distinct digital states.
A multistate memory cell comprising:
- one or more superconducting devices configured to maintain a quantized magnetic field representing a stored state of the multistate memory cell, the stored state from among a set of three or more distinct digital states;
- circuitry to increment the stored state represented by the quantized magnetic field in response a received increment pulses;
- and
- circuitry to reset the stored state represented the quantized magnetic field to a minimum state in response a received reset pulse.
A content-addressable memory comprising:
- a plurality of search inputs each configured to receive a signal representing a state of content to be searched, the content represented by a combination of the states represented by the plurality of received signals;
- a plurality of multistate memory cells each configured to maintain a quantized magnetic field representing a stored state from among a set of three or more distinct digital states;
- and
- a plurality of multistate comparators each having a first input coupled to read the stored state of a respective one of the plurality of multistate memory cells, a second input coupled to one of the plurality of search inputs, the comparator configured to either pass or block a test pulse based on comparing the state of the memory cell to the state received by the search input.
Dependencies are inferred from the claim text.