Memory block maintenance prioritization based on access frequency

A memory system, comprising:

• one or more memories storing processor-executable code;
• and
• one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the memory system to:
• perform a plurality of access operations to access data stored to a plurality of memory cells within the memory system;
• store, based at least in part on the plurality of access operations, information that indicates, for each logical block address of a plurality of logical block addresses of the memory system, a respective quantity of accesses associated with each logical block address within a threshold duration;
• perform, during an idle mode of the memory system, a first refresh of a first memory cell based at least in part on the information indicating that a first logical block address of the first memory cell is associated with a first quantity of accesses within the threshold duration that is greater than other quantities of accesses associated with other logical block addresses of the plurality of logical block addresses;
• and
• perform, during the idle mode of the memory system and after the first refresh, a second refresh of a second memory cell based at least in part on the information indicating that a second logical block address of the second memory cell is associated with a second quantity of accesses within the threshold duration that is less than the first quantity of accesses.

A method by a memory system, comprising:

• performing a plurality of access operations to access data stored to a plurality of memory cells within the memory system;
• storing, based at least in part on the plurality of access operations, information that indicates, for each logical block address of a plurality of logical block addresses of the memory system, a respective quantity of accesses associated with each logical block address within a threshold duration;
• and
• performing a refresh maintenance operation comprising a plurality of refreshes of the plurality of memory cells within the memory system, wherein the plurality of refreshes are performed in a refresh priority order that is based at least in part on the information.

A method by a memory system, comprising:

• performing a plurality of access operations to access data stored to a plurality of memory cells within the memory system;
• storing, based at least in part on the plurality of access operations, information that indicates, for each logical block address of a plurality of logical block addresses of the memory system, a respective quantity of accesses associated with each logical block address within a threshold duration;
• performing, during an idle mode of the memory system, a first refresh of a first memory cell based at least in part on the information indicating that a first logical block address of the first memory cell is associated with a first quantity of accesses within the threshold duration that is greater than other quantities of accesses associated with other logical block addresses of the plurality of logical block addresses;
• and
• performing, during the idle mode of the memory system and after the first refresh, a second refresh of a second memory cell based at least in part on the information indicating that a second logical block address of the second memory cell is associated with a second quantity of accesses within the threshold duration that is less than the first quantity of accesses.

A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to:

• perform a plurality of access operations to access data stored to a plurality of memory cells within the memory system;
• store, based at least in part on the plurality of access operations, information that indicates, for each logical block address of a plurality of logical block addresses of the memory system, a respective quantity of accesses associated with each logical block address within a threshold duration;
• and
• perform a refresh maintenance operation comprising a plurality of refreshes of the plurality of memory cells within the memory system, wherein the plurality of refreshes are performed in a refresh priority order that is based at least in part on the information.