Processor for configurable parallel computations

A processor receiving a system input data stream, the processor being included in a system that further comprises a host processor, the processor comprising:

• a data bus configured for receiving real time data, wherein at least a portion of the system input data stream is received over the data bus;
• a plurality of stream processors each configurable by the host processor to receive an input data stream and to provide an output data stream, wherein (i) the input data streams of selected one or more of the stream processors receive the system input data stream, and (ii) the stream processors each comprise a control circuit, a plurality of arithmetic logic circuits, and a processor bus, wherein (a) the control circuit is configurable by the host processor to control operations in the arithmetic logic circuits;
• and (b) each arithmetic logic circuit is individually memory-mapped for enablement to allow the arithmetic logic circuits to be enabled in a predetermined order over the processor bus by the host processor or the control circuit;
• and
• a plurality of configurable interconnection circuits connecting the stream processors, each configurable interconnection circuit being configurable by the host processor to selectively route the output data streams of the stream processors as input data streams of the stream processors, wherein the configurable interconnection circuits are configured by the control circuit in the course of the operations in the arithmetic logic circuits.