# US 2026/0133907 A1 · Memory device and method with pre-read acceleration techniques > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0133907 A1 - Document ID: US20260133907A1 - Status: Published application - Kind: A1 - Application number: 19/206,802 - Filed: 2025-05-13 - Published: 2026-05-14 - Earliest claimed: 2024-11-13 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yoojin KIM; Jinseong KIM; Jihoon NAM; Jihye PARK; Jinsu PARK; Yeongon CHO - Web page: https://patentgrep.com/patent/US20260133907A1 ## CPC - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible - G06F 12/0859: {with reload from main memory} - G06F 2212/1024: Latency reduction - G06F 2212/305: being part of a memory device, e.g. cache DRAM - G06F 2212/401: Compressed data - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory device performs determining whether a read request received from a host is hit in a cache in response to the read request, and at least one of operations for determining data corresponding to the read request in parallel in a memory processing unit. The memory device returns data obtained from a memory module through the memory processing unit to the host in a case of a cache miss, and returns data hit in the cache to the host in a case of a cache hit. ## Claims ### Claim 1 A memory device comprising: a cache configured to make a cache-hit determination, in response to a read request from a host, the cache-hit determination determining whether the read request results in a hit to the cache; a pre-request manager configured to provide a memory processing unit with a pre-request for performing at least one operation of operations for determining data corresponding to the read request before completion of the determination of whether the read request results in a hit in the cache, wherein the pre-request corresponds to the read request or is a copy of the read request; and the memory processing unit configured to perform the at least one operation in response to the reception of the pre-request, wherein, data obtained from a memory module through the memory processing unit based on the pre-request is returned to the host in a case of the cache-hit determination determining a cache miss has occurred, and data hit in the cache is returned to the host in a case of the cache-hit determination determining a cache hit. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the pre-request manager is configured to instruct the memory processing unit to abort an operation subsequent to the at least one operation in response to the cache-hit determination determining a cache hit for the read request. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the pre-request manager is configured to provide the memory processing unit with a read request comprising an abort flag value in response to the cache-hit determination of a cache hit determining a cache hit for the read request, and the memory processing unit is configured to remove a response corresponding to the read request comprising the abort flag value without subsequent processing of the response to the read request comprising the abort flag value in a memory response queue. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the pre-request manager is configured to notify the memory processing unit of aborting of the read request in response to the cache-hit determination determining a cache hit for the read request, and the memory processing unit is configured to remove the read request from a memory request queue or to deactivate the read request in the memory request queue. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the memory processing unit is configured to perform an operation subsequent to the at least one operation in response to the cache-hit determination determining a cache miss for the read request. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the at least one operation comprises a data loading operation corresponding to the read request, the data loading operation loading data from the memory module, and the memory processing unit is configured to start the data loading operation before the cache-hit determination is completed. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the memory processing unit is configured to: receive the data corresponding to the read request from the memory module before the cache-hit determination is completed; and in response to the cache-hit determination determining a cache miss for the read request, obtain data to be returned to the host based on data loaded from the memory module. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the at least one operation comprises an address translation operation for the read request, and the memory processing unit is configured to start the address translation operation for the read request before the cache-hit determination is completed. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the memory processing unit is configured to: perform translation of an address corresponding to the read request before the cache-hit determination is completed; and in response to the cache-hit determination determining a cache miss for the read request, load data from the memory module using the translated address and obtain data to be returned to the host using the loaded data. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the memory device is configured to update data, which is to be returned to the host, into the cache, in response to the cache-hit determination determining a cache miss for the read request. ### Claim 11 A method of operating a memory device, the method comprising: making a cache-hit determination for a read request received from a host in response to the read request; providing a memory processing unit with a pre-request for performing at least one operation of operations for determining data corresponding to the read request before completion of the cache-hit determination of the read request, wherein the pre-request corresponds to the read request or is a copy of the read request; performing the at least one operation in response to the reception of the pre-request; and returning data obtained from a memory module through the memory processing unit to the host in a case of the cache-hit determination determining a cache miss, and returning data hit in the cache to the host in a case of the cache-hit determination determining a cache hit. ### Claim 12 (depends on 11) The method of claim 11, wherein the returning of the data to the host comprises instructing the memory processing unit to abort an operation subsequent to the at least one operation in response to the cache-hit determination determining a cache hit for the read request. ### Claim 13 (depends on 11) The method of claim 11, wherein the returning of the data to the host comprises: providing the memory processing unit with a read request comprising an abort flag value in response to the cache-hit determination determining a cache hit occurring for the read request; and removing a response corresponding to the read request comprising the abort flag value without subsequent processing of the response to the read request comprising the abort flag value in a memory response queue. ### Claim 14 (depends on 11) The method of claim 11, wherein the returning of the data to the host comprises: notifying the memory processing unit of aborting of the read request in response to the cache-hit determination determining a cache hit occurring for the read request; and removing the read request from a memory request queue of the memory processing unit or deactivating the read request in the memory request queue. ### Claim 15 (depends on 11) The method of claim 11, wherein the returning of the data to the host comprises: performing, by the memory processing unit, an operation subsequent to the at least one operation in response to the cache-hit determination determining a cache miss for the read request. ### Claim 16 (depends on 11) The method of claim 11, wherein the at least one operation comprises a data loading operation corresponding to the read request, the data loading operation comprising loading the data corresponding to read request from the memory module, and the providing of the memory processing unit with the pre-request comprises starting the data loading operation by the memory processing unit before the cache-hit determination is completed. ### Claim 17 (depends on 11) The method of claim 11, wherein the performing of the at least one operation in response to the reception of the pre-request comprises receiving the data corresponding to the read request from the memory module before the cache-hit determining is completed, and the returning of the data to the host comprises, in response to the cache-hit determination determining a cache miss for the read request, obtaining data to be returned to the host based on data loaded from the memory module. ### Claim 18 (depends on 11) The method of claim 11, wherein the at least one operation comprises an address translation operation for the read request, and the providing of the memory processing unit with the pre-request comprises starting the address translation operation for the read request by the memory processing unit before the cache-hit determination is completed. ### Claim 19 (depends on 11) The method of claim 11, wherein the performing of the at least one operation in response to the reception of the pre-request comprises performing translation of an address corresponding to the read request before the cache-hit determination is completed, and the returning of the data to the host comprises, in response to the cache-hit determination determining a cache miss for the read request, loading data from the memory module using the translated address and obtaining data to be returned to the host using the loaded data. ### Claim 20 (depends on 11) The method of claim 11, wherein the returning of the data to the host comprises updating data to be returned to the host into the cache, in response to the cache-hit determination determining a cache miss for the read request. ### Claim 21 A method performed by a compressed memory device comprising a cache and a memory module storing compressed data, the method comprising: receiving, from a host, a read request for data, the read request comprising a host address; based on the read request, making a determination that a cache-hit occurs for the host address in the cache; based on receiving the read request, and before the determining of the cache-hit is completed, initiating operations to retrieve the data from memory module; and based on the determining that the cache-hit occurred, aborting or not completing the operations to retrieve the data from the memory module. ### Claim 22 (depends on 18) The method of claim 18, wherein the operations include translating the host address to a memory address in the memory module. ### Claim 23 (depends on 18) The method of claim 18, wherein the operations include decompressing the requested data from the memory module.