Enabling logical operations in low-power, double data rate (lpddr) memory
AssigneeQUALCOMM Incorporated
InventorsSang TRAN, Rongtian ZHANG
Life of this patent
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Abstract
A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input/output (I/O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers/demultiplexers. Each multiplexer/demultiplexer is coupled between a memory bank, a corresponding I/O block, one of the two multiplexers, and the accumulator.
Claims20
A memory apparatus, comprising:
- two independent subchannels of double data rate (DDR) memory, each subchannel comprising a plurality of memory banks, and an input/output (I/O) block having a plurality of meta data registers;
- and
- a processing unit comprising an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers/demultiplexers, each multiplexer/demultiplexer coupled between a memory bank, a corresponding I/O block, one of the two multiplexers, and the accumulator.
A memory processing method, comprising:
- selecting two inputs for an arithmetic logic unit (ALU), the two inputs selected from a first independent subchannel of double data rate (DDR) memory, a second independent subchannel of the DDR memory, an accumulator output, and/or internal static random access memory (SRAM);
- and
- performing vector operations on the two inputs with the ALU.
A non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor and comprising:
- program code to select two inputs for an arithmetic logic unit (ALU), the two inputs selected from a first independent subchannel of double data rate (DDR) memory, a second independent subchannel of the DDR memory, an accumulator output, and/or internal static random access memory (SRAM);
- and
- program code to perform vector operations on the two inputs with the ALU.
Dependencies are inferred from the claim text.