Data lane deskew and rate adaptation in a package containing multiple circuit dies
AssigneeKandou Labs, S.A.
InventorsPeter Korger Korger, Alexander Koch Koch
Life of this patent
Estimating the term…
Abstract
Methods and systems are described for performing multi-lane alignment and rate adaptation between tiles (1304, 1302) in a multi¬file package (1300), specifically exchanging alignment information (algn_found, rpcs_algn_ctl) across clock domains for different tiles (1304, 1302) based on a write tile clock (wr_tile_clk) generated from a local system clock (tx_clk) in a leader tile (1302), the write tile clock (wr_tile_clock) having a period equal to a common reference clock (refclk), the write tile clock (wr_tile_clock) corresponding to a pulse having a location within the period of the common reference clock (refclk) as determined by an active cycle of a counter.
Claims20
A method comprising:
- detecting alignment symbols in FIFOs of a plurality of data lanes of a plurality of tiles, the plurality of tiles comprising a leader tile and one or more follower tiles;
- determining an alignment symbol has been detected in the FIFO of every lane of every tile, and responsively generating an alignment found signal;
- generating a write tile clock from a local system clock, the write tile clock having a period equal to a period of a common reference clock, the write tile clock corresponding to a pulse having a location within the period of the common reference clock as determined by an active cycle of a counter,
- transmitting the alignment found signal to synchronization logic in each of the follower tiles responsive to the write tile clock;
- sampling the alignment found signal using the synchronization logic within each follower tile and the leader tile according to the common reference clock;
- synchronizing the alignment found signal to locally-generated system clocks for each tile of the plurality of tiles, and responsively setting a read pointer of the FIFO to a location containing the alignment symbol;
- and
- outputting data from each FIFO according to the locally-generated system clocks.
An apparatus comprising:
- alignment symbol detection logic configured to detect alignment symbols in FIFOs of a plurality of data lanes of a plurality of tiles, the plurality of tiles comprising a leader tile and one or more follower tiles;
- a write tile clock generator in the leader tile configured to generate a write tile clock from a local system clock, the write tile clock having a period equal to a period of a common reference clock, the write tile clock corresponding to a pulse having a location within the period of the common reference clock as determined by an active cycle of a counter;
- a multi-lane controller in the leader tile configured to determine an alignment symbol has been detected in the FIFO of every lane of every tile, to generate an alignment found signal, and to transmit the alignment found signal to synchronization logic in each of the plurality of tiles responsive to the write tile clock;
- the synchronization logic in each follower tile configured to sample the alignment found signal according to the common reference clock, and to synchronize the alignment found signal to locally-generated system clocks for each tile of the plurality of tiles;
- an alignment control state machine in each tile configured to set read pointers of each FIFOs in the tile to a location containing the alignment symbol;
- and
- the plurality of FIFOs configured to output data according to the locally-generated system clocks.
Dependencies are inferred from the claim text.