Voltage glitch detection
AssigneeNXP B.V.
InventorHyunsung Lee
Life of this patent
Estimating the term…
Abstract
The disclosure relates to a supply voltage glitch detection circuit including a first flip-flop having a data input, a clock input and an output; a delay circuit having an output connected to the data input of the first flip-flop; a first clock signal divider having a clock input connected to receive an inverted clock signal and an output connected to an input of the delay circuit; a second clock signal divider having a clock input connected to receive the clock signal and an output connected to the clock input of the first flip-flop, where the circuit is configured to cause a glitch detection signal output to change state upon a supply voltage of the circuit deviating to cause a change in a delay provided by the delay circuit.
Claims21
-15. (canceled)
A supply voltage glitch detection circuit comprising:
- a first flip-flop having a data input, a clock input and an output for providing a glitch detection signal;
- a delay circuit having an input and an output connected to the data input of the first flip-flop;
- a first clock signal divider having a clock input connected to receive an inverted clock signal and an output connected to the input of the delay circuit;
- a second clock signal divider having a clock input connected to receive the clock signal and an output connected to the clock input of the first flip-flop, and
- wherein the supply voltage glitch detection circuit is configured to cause the glitch detection signal to change state upon a supply voltage of the circuit deviating to cause a change in a delay provided by the delay circuit.
A method of detecting a supply voltage glitch using a detector circuit comprising:
- a first flip-flop having a data input, a clock input and an output for providing a glitch detection signal;
- a delay circuit having an input and an output connected to the data input of the first flip-flop;
- a first clock signal divider having a clock input connected to receive an inverted clock signal and an output connected to the input of the delay circuit;
- a second clock signal divider having a clock input connected to receive the clock signal and an output connected to the clock input of the first flip-flop, and
- wherein the delay circuit provides a delay of at least half a clock period of a clock signal with a supply voltage of the circuit at a nominal level and, when an increase in the supply voltage causes the delay to fall below half the clock period, the glitch detection signal changes state.
Dependencies are inferred from the claim text.