Chip packaging method and chip packaging structure

Abstract

Provided are a chip packaging method and a chip packaging structure. The method includes: arranging a spacer on at least one of a first surface of a package substrate and a second surface of a chip; arranging a first adhesive on at least one of the first surface, the second surface, or the spacer; bringing together the package substrate and the chip, to sandwich the spacer between the first surface and the second surface, and adhere the first surface to the second surface by the first adhesive; and curing the first adhesive. With the chip packaging structure generated based on the above-mentioned method, a shear displacement of the first adhesive can be increased under a given load to reduce an attachment area of the chip, ensuring a height of the first adhesive.

Dependencies are inferred from the claim text.