Chip on film package and electronic device including the same

An electronic device comprising:

• a printed circuit board;
• and
• a chip on film package comprising:
• an output pin on a first side of the chip on film package;
• and
• an input pin on a second side of the chip on film package, the input pin connecting the chip on film package and the printed circuit board;
• a substrate;
• a semiconductor chip on the substrate;
• first wires extending, on the substrate, to an edge of a first side of the substrate from a portion of the first wires overlapping with an edge of a first side of the semiconductor chip, wherein at least one of the first wires is connected to the output pin;
• second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip, wherein at least one of the second wires is connected to the input pin;
• first bumps connecting the first wires and the semiconductor chip;
• and
• first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip,
• wherein the first bumps comprise:
• first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip;
• and
• first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and
• wherein the first dummy patterns are respectively spaced apart from the first internal bumps in a second direction that is perpendicular to the first direction.

A chip on film package comprising:

• a substrate;
• a semiconductor chip on the substrate;
• first wires extending, on the substrate, to an edge of a first side of the substrate from a portion first of the first wires overlapping with an edge of a first side of the semiconductor chip;
• second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip;
• a first protection layer on at least a region of the first wires and the second wires;
• a second protection layer in a gap between the substrate and the semiconductor chip;
• first bumps connecting the first wires and the semiconductor chip;
• second bumps connecting the second wires and the semiconductor chip;
• and
• first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip,
• wherein the first bumps comprise:
• first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip;
• and
• first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and
• wherein each of the first dummy patterns comprise a quadrangular shape extending in a second direction that is perpendicular to the first direction, and the first dummy patterns are respectively spaced apart from the first internal bumps in the second direction.