Modem chip capable of performing cyclic redundancy check using internal memory, and system on chip including the modem chip

A modem chip capable of communicating with an external memory via a bus, the modem chip comprising:

• a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation including a first cyclic redundancy check and a second cyclic redundancy check with respect to a codeword including a transport block including a plurality of code blocks;
• and
• an internal memory configured to store data generated during the second cyclic redundancy check,
• wherein
• the HARQ processing circuit comprises:
• a code block processing circuit configured to decode the plurality of code blocks into decoded code blocks, perform the first cyclic redundancy check on the decoded code blocks, and store decoded code blocks, included in the decoded code blocks, that pass the first cyclic redundancy check into the external memory;
• and
• a codeword processing circuit configured to perform the second cyclic redundancy check on a decoded transport block by generating target blocks by respectively performing modular arithmetic with respect to each of the decoded code blocks,
• the plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and
• the internal memory includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence.

A system on chip comprising:

• a modem including an internal memory including a plurality of memory elements and configured to support a hybrid automatic repeat request (HARQ) function;
• and
• a processor configured to perform a certain data processing operation,
• wherein
• the modem is further configured to store, in the internal memory, intermediate data generated in a second cyclic redundancy check performed with respect to a transport block by using a target block corresponding to a decoded first code block that has passed a first cyclic redundancy check, based on memory management information corresponding to a first code block, and
• the memory management information includes an arrangement order of the first code block in a memory management group including the first code block and an address of a memory element allocated to the first code block.