High-speed digital to analog converter with high-speed interleaver and misalignment detector

A method, comprising:

• receiving, at a first pair of differential pair ports of an interleaver, a first data stream from a first sub-digital-to-analog converter (sub-DAC);
• receiving, at a second pair of differential pair ports of the interleaver, a second data stream from a second sub-DAC;
• alternately selecting each of the first pair of differential pair ports and each of the second pair of differential pair ports by a differential sampling frequency (FS)/2 (FS/2) frequency clock to generate output signals;
• combining, using a set of transmission wires, certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal;
• and
• outputting, using a first transmission wire and a second transmission wire with a defined degree of crossover to reduce differential FS/2 frequency clock feedthrough at a device output, the device output signal.

A device, comprising:

• an interleaver configured to receive a first data stream from a first sub-digital-to-analog converter (sub-DAC) and a second data stream from a second sub-DAC, and operate using a first clock, wherein each of the first sub-DAC and the second sub-DAC are configured to use a second clock;
• a replica interleaver configured to receive a first replica data stream from the first sub-DAC and a second replica data stream from the second sub-DAC, and operate at the second clock to generate replica output signals and replica select signals;
• and
• a multiplexor circuit configured to combine certain of the replica output signals and certain of the replica select signals to generate an alignment signal, wherein the alignment signal is used to align the second clock with the first clock.