Receiver circuit with parallel trigger circuitry

An integrated circuit, comprising:

• a plurality of receiver circuits;
• and
• additional circuitry coupled to the plurality of receiver circuits;
• wherein at least one of the receiver circuits comprises:
• first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit;
• and
• second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level;
• wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.

A method of manufacturing an integrated circuit, comprising:

• forming a plurality of receiver circuits;
• and
• forming additional circuitry;
• wherein the receiver circuits are coupled to the additional circuitry;
• and
• wherein forming each of one or more of the receiver circuits comprises:
• forming first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit;
• forming second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level;
• wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit, and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.