Ultra low power clock buffer

A low-power clock buffer circuit, comprising:

• a first push-pull stage including:
• a first PMOS transistor and a first NMOS transistor, each having a gate connected to receive a respective input signal, wherein drains of the first PMOS transistor and the first NMOS transistor are connected to form a first output node;
• a second push-pull stage including:
• a second PMOS transistor and a second NMOS transistor, each having a gate connected to receive the respective input signal, wherein drains of the second PMOS transistor and the second NMOS transistor are connected to form a second output node;
• and
• an output stage including:
• a third PMOS transistor having a gate connected to the second output node;
• and
• a third NMOS transistor having a gate connected to the first output node, wherein the first NMOS transistor and the second PMOS transistor are configured to be stronger than the first PMOS transistor and the second NMOS transistor, respectively, to control timing of signals at the first and second output nodes applied to the gates of the third PMOS and third NMOS transistors to reduce crowbar current in the output stage.

A method of operating a clock buffer circuit, the method comprising:

• receiving an input signal at an input stage;
• controlling a first current source to limit current flow through a first branch of the input stage;
• controlling a second current source to limit current flow through a second branch of the input stage;
• generating a first control signal at a first node between a first transistor and the first current source;
• generating a second control signal at a second node between a second transistor and the second current source;
• controlling a turn-on time of a third transistor in an output stage using the first control signal;
• controlling a turn-on time of a fourth transistor in the output stage using the second control signal;
• and
• generating an output signal at an output node formed by a connection between the third and fourth transistors.

A method of operating a clock buffer circuit, the method comprising:

• receiving respective input signals at a first push-pull stage and a second push-pull stage, the respective input signals being level-shifted versions of a common input signal;
• generating a first control signal at a first output node of the first push-pull stage by driving a first PMOS transistor and a first NMOS transistor using the respective input signals;
• generating a second control signal at a second output node of the second push-pull stage by driving a second PMOS transistor and a second NMOS transistor using the respective input signals;
• controlling relative strengths of the first and second push-pull stages such that a stronger NMOS transistor in the first push-pull stage and a stronger PMOS transistor in the second push-pull stage produce non-overlapping transitions of the first and second control signals;
• controlling a turn-on time of a third NMOS transistor in an output stage using the first control signal;
• controlling a turn-on time of a third PMOS transistor in the output stage using the second control signal;
• and
• generating an output signal at an output node formed by a connection between the third PMOS transistor and the third NMOS transistor..