Multiplexer circuit for a battery management system, and corresponding battery management system

A battery management system comprising:

• a multiplexer circuit (MUX) comprising:
• a first input terminal configured to couple to a first pin of a battery stack, a second input terminal configured to couple to a second pin of the battery stack, and a third input terminal configured to couple to a third pin of the battery stack;
• a first switch having a respective first terminal coupled to the first input terminal of the MUX, a second switch having a respective first terminal coupled to the second input terminal of the MUX, and a third switch having a respective first terminal coupled to the third input terminal of the MUX;
• and
• an analog front end (AFE) and selection circuit comprising:
• a first input terminal coupled to a second terminal of the first switch;
• a second input terminal coupled to a second terminal of the second switch;
• a third input terminal coupled to a second terminal of the third switch;
• a first output terminal configured to couple to a positive input of a first level shifter circuit;
• a second output terminal configured to couple to a negative input of the first level shifter circuit;
• a third output terminal configured to couple to a positive input of a second level shifter circuit;
• and
• a fourth output terminal configured to couple to a negative input of the second level shifter circuit;
• wherein each of the first, second, third, and fourth output terminals of the AFE and selection circuit is selectively couplable to any of the first, second, and third input terminals of the AFE and selection circuit;
• a first level shifter circuit having a positive input coupled to the first output terminal of the AFE and selection circuit, a negative input coupled to the second output terminal of the AFE and selection circuit, and an output port;
• a second level shifter circuit having a positive input coupled to the third output terminal of the AFE and selection circuit, a negative input coupled to the fourth output terminal of the AFE and selection circuit, and an output port;
• a first analog-to-digital converter (ADC) circuit having an input port coupled to the output port of the first level shifter circuit;
• and
• a second ADC circuit having an input port coupled to the output port of the second level shifter circuit.