Temperature compensation for analog memory cells in a neural network
AssigneeSilicon Storage Technology, Inc.
InventorsHOA VU, STANLEY HONG, HIEU VAN TRAN, THUAN VU, STEPHEN TRINH
Life of this patent
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Abstract
In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.
Claims20
A method comprising:
- determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal;
- and
- applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.
A circuit to generate a control gate and erase gate bias voltage, comprising:
- a reference memory cell comprising a control gate terminal, an erase gate terminal, and a bit line terminal;
- a current digital-to-analog converter to generate a current in response to a digital input and to apply the current to the bit line terminal;
- and
- an operational amplifier comprising an inverting terminal coupled to a bit line, a non-inverting terminal coupled to a reference voltage, and an output terminal providing a voltage to the control gate terminal and the erase gate terminal, wherein the voltage is output from the circuit as the control gate and erase gate bias voltage.
A method comprising:
- determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal;
- and
- applying voltages based on the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.
A method comprising:
- conducting a bias current through a reference memory cell;
- generating a bias voltage based on the bias current;
- and
- applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell during a read operation.
A method comprising:
- deriving a bias voltage from a combined control gate and erase gate temperature compensated voltage;
- and
- providing the bias voltage to control gate terminals and erase gate terminals of selected memory cells during a read operation.
A system comprising:
- an array of non-volatile memory cells arranged into rows and columns, each of the non-volatile memory cells comprising a control gate terminal and an erase gate terminal, wherein the control gate terminal of each non-volatile memory cell in a row is coupled to a control gate line and the erase gate terminal of each non-volatile memory cell in a row is coupled to an erase gate line;
- and
- a plurality of row circuits, each row circuit applying a voltage to a control gate line and an erase gate line coupled to a row of the array during a read operation of one or more non-volatile memory cells in the row.
Dependencies are inferred from the claim text.