Burst access memory and method of operating a burst access memory

Abstract

A burst access memory comprises a memory array comprising a plurality of memory macros comprising an array of memory cells in rows and columns. The memory cells in each column are connected by at least one local bit line. The array of memory cells and local bit lines define the memory macro. A plurality of global bit lines are each connectable to several corresponding local bit lines. A controller schedules a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros. The plurality of macro accesses are scheduled to start with a predefined delay in relation to each other. Each macro access is divided into a plurality of ordered sub-operations. Consecutive macro accesses are directed to different memory macros and different columns. Data for consecutive macro accesses are arranged in the different memory macros and columns to match the consecutive macro accesses.

Dependencies are inferred from the claim text.