Memory device comprising an array of memory cells

A memory device comprising an array of memory cells, each memory cell comprising M memory elements, where M is an integer greater than or equal to 1, and a switch configured to pass or block a current between two conduction electrodes of the switch, the memory cells being addressed by word lines, source lines and bit lines, wherein:

• a first of the conduction electrodes of each switch is coupled to a first electrode of each of the memory elements of a single one of the memory cells;
• each word line is coupled to a control electrode of each switch of a single and same column of memory cells;
• each source line is coupled to a second of the conduction electrodes of each switch of a single and same row of memory cells;
• each bit line is coupled to a second electrode of one of the memory elements of each memory cell of a single and same column of memory cells.