Electronic device comprising a memory element

A method for manufacturing a device including a plurality of memory cells arranged in an array with word lines and bit lines, each memory cell including a memory element made of a phase-change material and two fin field-effect transistors for selecting the memory element, each transistor comprising first and second conduction nodes and a gate, the memory element including two terminals, wherein:

• both transistors of a same memory cell are connected to each other by their first conduction nodes, the first conduction nodes being in turn connected to a first terminal of the memory element;
• the memory elements of a same bit line are all connected to each other by their second terminals;
• both transistors of the memory cells in a same word line are all connected to each other, by their gates;
• each memory cell is connected to two source lines, the two source lines being connected to two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line,
• the method including the steps of:
• forming fins in a semiconductor substrate, fins being formed by pairs;
• epitaxially forming a semiconductive layer;
• and
• doping the semiconductive layer so as to form regions among which first regions correspond to source regions, and second regions correspond to drain regions, a drain region being common to both transistors of the same memory cell and a source region being common to two transistors of two neighboring memory cells.

A method, comprising:

• applying, in a memory array including a plurality of memory cells arranged in a plurality of bitlines and a plurality of wordlines, a first non-zero potential on a first bit line of the plurality of bitlines of a memory array and a zero potential on the other bit lines of the plurality of bitlines of the memory array, each memory cell including a memory element of a phase-change material and including a first terminal and a second terminal and two fin field-effect transistors for selecting the memory element, each transistor including first and second conduction nodes and a gate, wherein:
• both transistors of a same memory cell are connected to each other by their first conduction nodes, the first conduction nodes being connected to a first terminal of the memory element;
• the memory elements of a same bit line are all connected to each other by their second terminals;
• both transistors of memory cells of a same word line are all connected to each other by their gates;
• each memory cell is connected to two source lines, the two source lines being connected to the two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line;
• and
• each transistor is disposed in and on a pair of two parallel and neighboring fins disposed in a semiconductor substrate;
• applying a second non-zero potential on a first word line of the plurality of wordlines and a zero potential on the other word lines of the plurality of wordlines;
• applying a zero potential to two source lines coupled to the memory cells of the first word line and a third non-zero potential to the other source lines.