Convolution Circuit, Convolution Computing Method, Chip, and Electronic Device

A method comprising:

• receiving a plurality of input feature maps;
• receiving weight parameters and computing constants that are pre specified for the plurality of input feature maps, wherein the computing constants are based on the weight parameters;
• transmitting one of the input feature maps and one of the weight parameters to each multiplier of a plurality of multipliers of a convolution circuit;
• performing an operation through a plurality of precoders, a plurality of encoder groups, and an adder tree circuit that are in the plurality of multipliers to obtain a corresponding operation result;
• accumulating operation results of the plurality of multipliers through a first adder of the convolution circuit to obtain first data;
• transmitting the computing constant to a second adder of the convolution circuit;
• and
• adding the first data and the computing constant through the second adder to obtain an output feature map.

A chip comprising:

• a circuit board;
• and
• a convolution circuit disposed on the circuit board, wherein the convolution circuit comprises:
• a plurality of multipliers, wherein each of the multipliers comprises:
• a plurality of precoders;
• a plurality of encoder groups coupled to the plurality of precoders in a one to one correspondence and comprising a plurality of output ends;
• and
• an adder tree circuit comprising:
• a plurality of adder tree input lines, wherein a first quantity of the plurality of output ends equals a second quantity of the plurality of adder tree input lines, and wherein the plurality of output ends is coupled to the plurality of adder tree input lines in a one to one correspondence;
• and
• a plurality of output lines;
• a first adder coupled to the plurality of multipliers and coupled to the adder tree circuit through the plurality of output lines;
• and
• a second adder coupled to the first adder, wherein the second adder comprises:
• a plurality of adder input ends, wherein a first adder input end in the plurality of adder input ends is configured to be coupled to a memory, and wherein a second adder input end in the plurality of adder input ends is configured to be coupled to the first adder;
• and
• an adder output end.