Memory device stack availability

An assembly, comprising:

• an external command/address (CA) interface to receive commands and addresses from a device external to the assembly;
• a first memory integrated circuit coupled to the external CA interface and comprising a first memory array, a first data interface, a first above parity interface, a first below parity interface, and first parity calculation circuitry;
• a second memory integrated circuit coupled to the external CA interface and being stacked with the first memory integrated circuit, the second memory integrated circuit comprising a second memory array, a second data interface, a second above parity interface, a second below parity interface, and second parity calculation circuitry, the second below parity interface being electrically coupled to the first above parity interface, the second parity calculation circuitry to calculate first parity information based on first information received via the second below parity interface and second information received via the second data interface;
• and
• a third memory integrated circuit coupled to the external CA interface and comprising a third memory array and a third below parity interface to receive the first parity information, the third memory integrated circuit to store, in the third memory array, the first parity information.