Process for manufacturing a silicon single crystal, and semiconductor wafer made of single-crystal silicon
AssigneeSiltronic AG
InventorsWalter HEUWIESER, Karl MANGELBERGER
Life of this patent
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Abstract
A method produces a single crystal of silicon by pulling the single crystal from a melt. The melt is in a crucible and includes phosphorus and boron as dopants in a ratio of not more than 0.41. The boron is in the melt with a concentration of 5.0×1014 to 2.2×1015 atoms/cm3. The single crystal has a cylindrical section having a diameter of at least 300 mm, which is surrounded by a heat shield while pulled from the melt. A lower edge of the heat shield is further than 18 mm from a melt surface. The single crystal is pulled at 8-13 rpm. A horizontal magnetic field is also applied to the melt, with a magnetic flux density of the horizontal magnetic of 2000-3000 Gs.
Claims6
A method of producing a single crystal of silicon, the method comprising:
- pulling the single crystal from a melt, the melt being present in a crucible and comprising phosphorus and boron as dopants in a ratio of not more than 0.41, the boron being in the melt with a concentration of not less than 5.0×1014 atoms/cm3 and not more than 2.2×1015 atoms/cm3, and the single crystal having a cylindrical section having a diameter of at least 300 mm, having a length, and being surrounded by a heat shield in a course of the pulling the single crystal from the melt, and a lower edge of the heat shield having a distance of not less than 18 mm from a surface of the melt, the pulling of the single crystal being at a speed of not less than 8 rpm and not more than 13 rpm;
- and
- applying a horizontal magnetic field to the melt, a magnetic flux density of the horizontal magnetic field being not less than 2000 Gs and not more than 3000 Gs.
A semiconductor wafer of monocrystalline silicon having a diameter of at least 300 mm, the semiconductor wafer being predominantly p-doped, the semiconductor wafer comprising phosphorus and boron as dopants, wherein a specific electrical resistance from a center up to an edge of the semiconductor wafer varies by not more than 1%, based on a smallest resistance, and taking account of an edge exclusion of 6 mm.
Dependencies are inferred from the claim text.