Isolation structure for n epitaxy-based silicon carbide device, and n epitaxy-based silicon carbide high and low voltage integrated device and preparation method therefor

An N epitaxy-based silicon carbide high and low voltage integrated device, comprising:

• an isolation structure, wherein the isolation structure comprises an N-type substrate, an N-type drift region is arranged on the N-type substrate, a first isolation trench-in which an oxide is deposited and a second isolation trench in which the oxide is deposited are arranged on the N-type drift region to form a high-voltage region, a low-voltage region and a level shift region, a second P-type doped region is arranged at a bottom of the low-voltage region and a bottom of the level shift region, a second N-type doped region is arranged on the second P-type doped region in the low-voltage region, and back-to-back PN junctions are formed by the N-type drift region-the second P-type doped region in the low-voltage region, and the second N-type doped region;
• a power DMOS device is arranged in the high-voltage region, low-voltage devices are arranged in the low-voltage region, and a high-voltage LDMOS device is arranged in the level shift region;
• a sixth N-type heavily doped region is arranged on the second N-type doped region, a third epitaxial layer is arranged on the second P-type doped region-in the level shift region, a third N-type doped region is arranged on the third epitaxial layer, a seventh N-type heavily doped region used as a drain of the high-voltage LDMOS device is arranged on the third N-type doped region, and the sixth N-type heavily doped region is connected to the seventh N-type heavily doped region by means of a fifth drain metal electrode to control a potential of the second N-type doped region.

A preparation method for an N epitaxy-based silicon carbide high and low voltage integrated device, comprising the following steps:

• acquiring a silicon carbide N-type substrate;
• epitaxially growing an N-type drift region on one surface of the silicon carbide N-type substrate;
• performing ion implantation on the N-type drift region to form a second P-type doped region, a first P-type doped region and first N-type doped regions,
• growing a P-type epitaxial layer on surfaces of the second P-type doped region, part of the N-type drift region, the first P-type doped region and the first N-type doped regions, and forming a first epitaxial layer and a third epitaxial layer;
• performing ion implantation on the third epitaxial layer above the second P-type doped region to form a third N-type doped region and a second N-type doped region;
• then, performing ion implantation on the third N-type doped region to form a third P-type doped region and a fourth P-type doped region;
• performing ion implantation on the first epitaxial layer above the first N-type doped regions, the second N-type doped region, the third P-type doped region, the fourth P-type doped region and the third epitaxial layer to form a first P-type heavily doped region, a second P-type heavily doped region, a third P-type heavily doped region, a fourth P-type heavily doped region, a fifth P-type heavily doped region, a sixth P-type heavily doped region, and a seventh P-type heavily doped region;
• performing ion implantation to form first N-type heavily doped regions, a number of which is twice that of the first P-type heavily doped region, in the first epitaxial layer above the first N-type doped regions, form a second N-type heavily doped region and a sixth N-type heavily doped region in the second N-type doped region, form a third N-type heavily doped region and a fourth N-type heavily doped region in the third P-type doped region, form a fifth N-type heavily doped region in the fourth P-type doped region, form a seventh N-type heavily doped region in the third N-type doped region, and form an eighth N-type heavily doped region in the third epitaxial layer;
• performing wet oxidation after high-temperature annealing, growing a gate-oxide dielectric on a surface of a current local device structure, and taking the gate-oxide dielectric above the second N-type doped region between the second P-type heavily doped region and the third P-type heavily doped region as a second planar gate-oxide dielectric, the gate-oxide dielectric above the third P-type doped region between the third N-type heavily doped region and the fourth N-type heavily doped region as a third planar gate-oxide dielectric, and the gate-oxide dielectric above the third epitaxial layer between the third N-type doped region and the eighth N-type heavily doped region as a fourth planar gate-oxide dielectric;
• respectively, depositing a second polysilicon gate, a third polysilicon gate and a fourth polysilicon gate on the second planar gate-oxide dielectric, the third planar gate-oxide dielectric and the fourth planar gate-oxide dielectric;
• respectively, etching trenches between the first epitaxial layer and the second N-type doped region, between the second N-type doped region and the third epitaxial layer, and in the first epitaxial layer above the first P-type doped region and depositing an oxide to form a first isolation trench, a second isolation trench and an oxide trench, performing etching in the oxide trench and forming a first trench gate-oxide dielectric, and depositing polysilicon in the first trench gate-oxide dielectric to form a first polysilicon gate and
• depositing an oxide layer on a device surface in a current state to form an interlayer dielectric, etching through-holes in the interlayer dielectric and depositing a metal layer on the interlayer dielectric, and etching the metal layer to form a first source metal electrode, a second drain metal electrode, a second source metal electrode, a third drain metal electrode, a third source metal electrode, a fourth drain metal electrode, a first gate metal electrode, a fourth source metal electrode, a fifth drain metal electrode and a fifth source metal electrode;
• depositing metal in a high-voltage region on the other surface of the N-type substrate, and forming a first drain metal electrode.