Apparatus with integrated planar mosfet and integrated planar schottky barrier diode

An apparatus comprising:

• a volume of semiconductor material including a first end, a second end, a first side, and a second side;
• an integrated planar metal oxide semiconductor field-effect transistor including—
• a first transistor side located at the first side of the volume of semiconductor material, the first transistor side including—
• a first well located at the first end of the volume of semiconductor material, and
• a first gate over at least a portion of the first well, and
• a second transistor side located at the second side of the volume of semiconductor material, the second transistor side including—
• a second well located at the first end of the volume of semiconductor material, and
• a second gate over at least a portion of the second well;
• and
• a junction field effect transistor neck region of the volume of semiconductor material located between the first transistor side and the second transistor side;
• and
• an integrated planar Schottky barrier diode including a Schottky material located at the first end of the volume of semiconductor material over at least a portion of the junction field-effect transistor neck region between and spaced apart from the first and second transistor sides.

A method comprising:

• growing a volume of semiconductor material including a first end, a second end, a first side, and a second side, and including a junction field effect transistor neck region;
• forming a first transistor side of an integrated planar metal oxide semiconductor field-effect transistor at the first side of the volume of semiconductor material and adjacent to the junction field effect transistor neck region, wherein the operation of forming the first transistor side includes—
• implanting a first P-well at the first end of the volume of semiconductor material, and
• forming a first gate, wherein the operation of forming the first gate includes—
• depositing a first layer of dielectric material over at least a portion of the first P-well, and
• depositing a first layer of doped polysilicon over the first layer of dielectric material;
• and
• making an integrated planar Schottky barrier diode including adding a Schottky material at the first end of the volume of semiconductor material over at least a portion of the junction field-effect transistor neck region adjacent and spaced apart from the first transistor side.