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US 2026/0122932 A1Published application
Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsKeonhee Park, Yeonjin Lee, Haewook Jeong
Life of this patent
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Abstract
Provided is a semiconductor device including a buffer die configured to communicate with an external device, a memory die stack including a plurality of memory dies stacked on the buffer die and connected to the buffer die through a plurality of through silicon vias, and a capacitor arranged on an upper portion of an uppermost memory die among the plurality of memory dies, wherein the capacitor surrounds at least some surfaces of the plurality of memory dies, when viewed in a top down view.
Claims20
A semiconductor device comprising:
- a buffer die configured to communicate with an external device;
- a memory die stack including a plurality of memory dies stacked on the buffer die and connected to the buffer die through a plurality of through silicon vias;
- and
- a capacitor arranged on an upper portion of an uppermost memory die among the plurality of memory dies,
- wherein the capacitor surrounds at least some surfaces of the plurality of memory dies, when viewed in a top down view.
2 more elements
A semiconductor device comprising:
- a memory device comprising a buffer die configured to communicate with an external device and a memory die stack including a plurality of memory dies stacked on the buffer die and connected to the buffer die through a plurality of through silicon vias;
- and
- a capacitor electrically connected to the memory device and covering at least a portion of the memory device,
- wherein the capacitor comprises:
- a first electrode;
- a second electrode;
- and
- a dielectric arranged between the first electrode and the second electrode.
5 more elements
A semiconductor device comprising:
- a memory device comprising a buffer die configured to communicate with an external device and a memory die stack including a plurality of memory dies stacked on the buffer die and connected to the buffer die through a plurality of through silicon vias;
- a system on chip including a processor;
- an interposer substrate connecting the memory device to the system on chip;
- and
- a capacitor electrically connected to the memory device and covering at least a portion of each of the memory device and the system on chip.
2 more elements
Dependencies are inferred from the claim text.