Large memory window vertical nand ferroelectric charge pumping field effect transistor for high-density and low-power storage

A nonvolatile memory device comprising:

• a semiconductor substrate;
• a gate stack disposed on the semiconductor substrate, the gate stack comprising:
• an interfacial dielectric layer disposed on the semiconductor substrate;
• a ferroelectric dielectric layer disposed on the interfacial dielectric layer, the ferroelectric dielectric layer being configured to undergo polarization switching in response to an applied electric field;
• a charge trapping layer disposed on the ferroelectric dielectric layer;
• and
• a gate electrode disposed on the charge trapping layer,
• wherein application of a programming pulse to the gate electrode generates an electric field across the ferroelectric dielectric layer,
• wherein the electric field causes the polarization switching within the ferroelectric dielectric layer,
• wherein the charge trapping layer is configured to receive charge from the gate electrode during application of a programming pulse,
• wherein the polarization switching facilitates injection of charge from the gate electrode into the charge trapping layer, and
• wherein the charge trapping layer is configured to retain the injected charge to contribute to a shift in threshold voltage of the nonvolatile memory device.