Data sending circuit, data receiving circuit, and electronic device
AssigneeCXMT Corporation
InventorMIYAMOTO KENICHI
Life of this patent
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Abstract
A data sending circuit comprises a parallel-to-serial conversion circuit, a multi-level modulation circuit and a first transmission path; the parallel-to-serial conversion circuit is configured to convert a plurality of parallel initial data signals into serial data combinations, wherein each data combination comprises an n-bit data signal; the multi-level modulation circuit is configured to generate and output a target data signal on the basis of each data combination; and the first transmission path is coupled with the multi-level modulation circuit and is configured to transmit the target data signal to a second chip.
Claims19
A data transmitting circuit, applied to a first chip, the data transmitting circuit comprising:
- a parallel-to-serial conversion circuit, configured to receive a plurality of parallel initial data signals, and convert, based on an initial clock signal, the plurality of parallel initial data signals into a serial data combination, wherein the data combination comprises an n-bit data signal, and n is an integer greater than 1;
- a multi-level modulation circuit, coupled to the parallel-to-serial conversion circuit and configured to receive and, based on each data combination, generate and output one target data signal, wherein if the n-bit data signal in the data combination forms different signal value combinations, voltage values of resulting target data signals are different;
- and
- a first transmission path, coupled to the multi-level modulation circuit and configured to output the target data signal from the first chip.
10. A data receiving circuit, applied to a second chip, the data receiving circuit comprising:
- a third transmission path, configured to receive a target data signal transmitted to the second chip;
- a data comparison circuit, coupled to the third transmission path and configured to receive (2n - 1) reference voltages and the target data signal, compare a voltage value of each of the reference voltages with a voltage value of the target data signal, and generate and output (2n - 1) comparison signals;
- and
- a logic processing circuit, coupled to the data comparison circuit and configured to perform logic processing on the (2n - 1) comparison signals to generate and output a data combination, wherein each data combination comprises an n-bit data signal, and n is an integer greater than 1.
Dependencies are inferred from the claim text.