Manufacturing method of an input circuit of a flip-flop

An input circuit of a flip flop, comprising:

• a first first gate strip, extending in a first direction, wherein the first first gate strip is configured to be a gate terminal of a first PMOS;
• a second first gate strip, extending in the first direction, wherein the first first gate strip and the second first gate strip are arranged in the first direction, and the second first gate strip is configured to be a gate terminal of a first NMOS;
• a second gate strip, disposed immediately adjacent to the first first gate strip and the second first gate strip, wherein the second gate strip is configured to be a co-gate terminal of a second PMOS and a second NMOS, the first PMOS and the second PMOS share a doping region as a co-drain terminal, and the first NMOS and the second NMOS share a doping region as a co-drain terminal;
• a first third gate strip, extending in the first direction, wherein the first third gate strip is disposed immediately adjacent to the second gate strip and configured to be a gate terminal of a third PMOS, and the second PMOS and the third PMOS share a doping region as a co-source terminal;
• a second third gate strip, extending in the first direction, wherein the first third gate strip and the second third gate strip are arranged in the first direction, the second third gate strip is disposed immediately adjacent to the second gate strip and configured to be a gate terminal of the third NMOS, and the second NMOS and the third NMOS share a doping region as a co-source terminal.

An input circuit of a flip-lop, comprising:

• a first multiplexer, comprising a first PMOS, a second PMOS and a third PMOS;
• a second multiplexer, comprising a first NMOS, a second NMOS and a third NMOS;
• a clock receiving NMOS, wherein a first clock signal is directed to a gate terminal of the clock receiving NMOS, and a source terminal of the clock receiving NMOS is coupled to the second multiplexer;
• a clock receiving PMOS, wherein a second clock signal is directed to a gate terminal of the clock receiving PMOS, a source terminal of the clock receiving PMOS is coupled to the first multiplexer, and a drain terminal of the clock receiving PMOS is coupled to a drain terminal of the clock receiving NMOS;
• a first gate strip, wherein the first gate strip is configured to be a co-gate terminal of the first PMOS and the first NMOS;
• a second gate strip, disposed immediately adjacent to the first gate strip, wherein the second gate strip is configured to be a co-gate terminal of the second PMOS and the second NMOS, the first PMOS and the second PMOS share a doping region as a co-source terminal, and the first NMOS and the second NMOS share a doping region as a co-source terminal.