Memory Device with Low Wire Resistance and Method of Manufacturing the Same

Abstract

A memory device includes a plurality of memory cells, a word line, a plurality of bit lines, and a plurality of source lines. Each memory cell includes an one-time programmable (OTP) element and a plurality of select transistors. The word line is connected to gate terminals of the select transistors of a memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connects second source/drain terminals of the select transistors of the memory cell to a second node. A method for manufacturing the memory device is also disclosed.

Dependencies are inferred from the claim text.