US 2026/0120767 A1Published application

Semiconductor memory device

AssigneesTower Partners Semiconductor Co., Ltd., Tower Semiconductor Ltd.

InventorsHiroshige HIRANO, Hiroaki KURIYAMA, Atsushi NOMA, Evgeny PIKHAY, Yakov ROIZIN

Life of this patent

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Abstract

A semiconductor memory device includes a plurality of memory cells formed on a semiconductor substrate. Each of the memory cells includes a first floating gate transistor (TFG1), a second floating gate transistor (TFG2), a first erasing element, a second erasing element, and a memory cell selection transistor. A gate of TFG1 is electrically coupled to a gate of the first erasing element. A gate of TFG2 is electrically coupled to a gate of the second erasing element. A source of TFG1 is electrically coupled to a drain of the memory cell selection transistor. A source of TFG2 is electrically coupled to the drain of the memory cell selection transistor or a drain of TFG1.

Claims12

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells formed on a semiconductor substrate,
wherein
each of the memory cells includes a first floating gate transistor, a second floating gate transistor, a first erasing element, a second erasing element, and a memory cell selection transistor,
a gate of the first floating gate transistor is electrically coupled to a gate of the first erasing element,
a gate of the second floating gate transistor is electrically coupled to a gate of the second erasing element,
a source of the first floating gate transistor is electrically coupled to a drain of the memory cell selection transistor, and
a source of the second floating gate transistor is electrically coupled to the drain of the memory cell selection transistor or a drain of the first floating gate transistor.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/006,014Filed 30 Dec 2024
Priority: JP 2024-19013029 Oct 2024
Published: 30 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 16/0441
Comprising cells containing floating gate transistors: comprising cells containing multiple floating gate devices, e.g. separate read-and-write…
G11C 16/0425
Comprising cells containing floating gate transistors: comprising cells containing a merged floating gate and select transistor
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
G11C 16/045
Comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates: floating…