Dual mode inverter-based write termination circuit, method thereof, and devices having the same
AssigneeUIF (University Industry Foundation), Yonsei University
InventorsSEONG-OOK JUNG, DO YOON LIM, DONG HAN KO, WAN GYU LEE
Life of this patent
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Abstract
A memory device includes: a memory cell, a reference memory cell, and a dual mode inverter-based write termination circuit including a write driver for writing data to the memory cell, the dual mode inverter-based write termination circuit detecting the completion of writing data to the memory cell and terminating the operation of the write driver, and also sequentially receiving an output signal of the reference memory cell and an output signal of the memory cell through one input node to sense and amplify the data stored in the memory cell.
Claims18
A dual mode inverter-based write termination circuit comprising:
- a first inverter including a first input node configured to receive a first input signal and a first output node configured to output a first output signal;
- a second inverter including a second input node and a second output node;
- a second switch connected between the first output node and the second input node;
- a pull-up circuit configured to pull up the second input node to a first voltage in response to a first control signal;
- a pull-down circuit configured to pull down the second input node to a second voltage in response to a second control signal;
- and
- a voltage maintenance circuit configured to maintain a second output signal of the second output node.
A memory device comprising:
- a memory cell;
- a reference memory cell;
- and
- a dual mode inverter-based write termination circuit including a write driver configured to write data to the memory cell,
- wherein the dual mode inverter-based write termination circuit is configured to detect completion of writing data to the memory cell and terminate the operation of the write driver, and also sequentially receive an output signal of the reference memory cell and an output signal of the memory cell through one first input node to sense and amplify the data stored in the memory cell.
A memory system comprising:
- a processor configured to output data;
- and
- a memory device configured to receive the data,
- the memory device comprising:
- a memory cell;
- a reference memory cell;
- and
- a dual mode inverter-based write termination circuit including a write driver configured to write data to the memory cell,
- wherein the dual mode inverter-based write termination circuit is configured to detect completion of writing data to the memory cell and terminate an operation of the write driver, and also sequentially receive an output signal of the reference memory cell and an output signal of the memory cell through one first input node to sense and amplify the data stored in the memory cell.
Dependencies are inferred from the claim text.