Tiled compute and programmable logic array
AssigneeXilinx, Inc.
InventorsBrian C. GAIDE, Sneha Bhalchandra DATE, Juan J. NOGUERA SERRA
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Abstract
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.
Claims1
A method of fabricating a stacked integrated circuit device, the method comprising:
- disposing a first die including a first plurality of data processing engines arranged in a first array with a second die including a second plurality of data processing engines arranged in a second array such that the corresponding data processing engines in the first and second arrays are vertically aligned;
- and
- hybrid bonding the first die to the second die to form a stack of dies in which the aligned data processing engines are electrically coupled.
Dependencies are inferred from the claim text.