Memory systems and techniques with support for sparse neural network computations

A buffer chip to:

• obtain, from a cache of the buffer chip, a first index associated with positions of a plurality of elements of a sparse matrix (SM) along a first dimension of the SM;
• obtain, from one or more memory units, a second index associated with positions of the plurality of the elements of the SM along a second dimension of the SM;
• obtain, using the first index and the second index, memory addresses of the plurality of the elements of the SM stored in the one or more memory units;
• and
• retrieve, based on the memory addresses, the plurality of the elements of the SM from the one or more memory units.

A method comprising:

• obtaining, using a buffer chip of a memory system, a first index associated with positions of a plurality of elements of a sparse matrix (SM) along a first dimension of the SM;
• obtaining, using the buffer chip of the memory system, a second index associated with positions of the plurality of the elements of the SM along a second dimension of the SM;
• processing, using the buffer chip of the memory system, the first index and the second index to obtain memory addresses of the plurality of the elements of the SM stored in one or more memory units;
• and
• retrieving, based on the memory addresses, the plurality of the elements of the SM from the one or more memory units.