Hardware apparatuses and methods for memory corruption detection
AssigneeIntel Corporation
InventorsTomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
Claims36
A processor comprising:
- first circuitry to decode an instruction, the instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [60:57];
- and
- second circuitry coupled with the first circuitry, the second circuitry, to perform operations associated with the instruction, including to:
- access a 4-bit value corresponding to the 128-bit block of data;
- determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data;
- and
- generate a fault when the 4-bit value from the 64-bit pointer does not match the 4-bit value corresponding to the 128-bit block of data.
A processor comprising:
- first circuitry to decode an instruction, the instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a value in a field, the field more significant than the address and not including at least one most significant bit of the 64-bit pointer;
- and
- second circuitry coupled with the first circuitry, the second circuitry, to perform operations associated with the instruction, including to:
- access a value corresponding to the 128-bit block of data;
- determine whether the value from the 64-bit pointer matches the value corresponding to the 128-bit block of data;
- and
- generate a fault when the value from the 64-bit pointer does not match the value corresponding to the 128-bit block of data.
A processor comprising:
- first circuitry to decode a load instruction, the load instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a value in a field, the field more significant than the address and not including at least one most significant bit of the 64-bit pointer;
- and
- second circuitry coupled with the first circuitry, the second circuitry, to perform operations associated with the load instruction, including to:
- determine whether the value from the 64-bit pointer matches a value from the memory corresponding to the 128-bit block of data;
- load the 128-bit block of data from the memory when the value from the 64-bit pointer matches the value from the memory;
- and
- generate a fault when the value from the 64-bit pointer does not match the value from the memory.
A non-transitory machine-readable storage media storing instructions that when executed cause a machine to perform operations, including to:
- receive a request to allocate a block of memory from an application;
- allocate the block of memory;
- generate a value;
- generate a 64-bit pointer, the 64-bit pointer including an address to a 128-bit portion of the block of memory, and the 64-bit pointer including a copy of the value in a field, the field more significant than the address and not including at least one most significant bit of the 64-bit pointer;
- store a copy of the value in an entry of a table in memory, the entry corresponding to the 128-bit portion of the block of memory;
- and
- provide the 64-bit pointer including the address and the copy of the value to the application.
Dependencies are inferred from the claim text.