Method of routing traces of an interconnect structure

A processing device for routing traces of an interconnect structure, comprising:

• a memory device;
• and
• processing circuitry coupled to the memory device and configured to:
• derive first capacity information of a first plurality of routing nodes in a first area of the interconnect structure, each routing node of the first plurality of routing nodes being associated with a corresponding track sequence index of a plurality of track sequence indexes, the first plurality of routing nodes and two virtual routing boundaries defining a first plurality of routing edges, and the first capacity information indicating one or more passing track sequence indexes for, or a number of traces accommodable by, each routing edge of a subset of the first plurality of routing edges;
• generate a first plurality of predicted traces connecting the first plurality of routing nodes based on the first capacity information;
• derive second capacity information of a second plurality of routing nodes in a second area of the interconnect structure, each routing node of the second plurality of routing nodes being associated with a corresponding track sequence index of the plurality of track sequence indexes, the second plurality of routing nodes and the two virtual routing boundaries defining a second plurality of routing edges, and the second capacity information indicating one or more passing track sequence indexes for, or a number of traces accommodable by, each routing edge of a subset of the second plurality of routing edges;
• generate a second plurality of predicted traces connecting the second plurality of routing nodes based on the second capacity information;
• and
• generate a plurality of traces connecting the first plurality of routing nodes and the second plurality of routing nodes based on the first plurality of predicted traces and the second plurality of predicted traces.

A non-transitory computer-readable medium that stores instructions which, when executed by processing circuitry of a processing device, cause the processing device to:

• derive first capacity information of a first plurality of routing nodes in a first area of an interconnect structure, each routing node of the first plurality of routing nodes being associated with a corresponding track sequence index of a plurality of track sequence indexes, the first plurality of routing nodes and two virtual routing boundaries defining a first plurality of routing edges, and the first capacity information indicating one or more passing track sequence indexes for, or a number of traces accommodable by, each routing edge of a subset of the first plurality of routing edges;
• generate a first plurality of predicted traces connecting the first plurality of routing nodes based on the first capacity information;
• derive second capacity information of a second plurality of routing nodes in a second area of the interconnect structure, each routing node of the second plurality of routing nodes being associated with a corresponding track sequence index of the plurality of track sequence indexes, the second plurality of routing nodes and the two virtual routing boundaries defining a second plurality of routing edges, and the second capacity information indicating one or more passing track sequence indexes for, or a number of traces accommodable by, each routing edge of a subset of the second plurality of routing edges;
• generate a second plurality of predicted traces connecting the second plurality of routing nodes based on the second capacity information;
• and
• generate a plurality of traces of the interconnect structure connecting the first plurality of routing nodes and the second plurality of routing nodes based on the first plurality of predicted traces and the second plurality of predicted traces.