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US 2026/0113176 A1Published application
Receiver with Flexible Link Synchronization
AssigneeTexas Instruments Incorporated
InventorsJaiganesh Balakrishnan, Kandalla Krishna, Aravind Vijayakumar, Goutham Ramesh
Life of this patent
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Abstract
A receiver includes: a PHY layer; and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling factor; and execute link synchronization operations based on the mismatch metric.
Claims20
A receiver comprising:
- a PHY layer;
- and
- a processor coupled to the PHY layer and configured to:
- receive a set of data bits from the PHY layer;
- compare each bit of the set of data bits to a respective bit of a sync pattern to detect a corresponding bit mismatch;
- determine a mismatch metric based on the corresponding bit mismatch;
- and
- execute link synchronization operations based on the mismatch metric.
5 more elements
A method comprising:
- receiving a set of data bits;
- comparing each bit of a set of data bits to a respective bit of a sync pattern to detect a corresponding bit mismatch;
- determining a mismatch metric based on the corresponding bit mismatch;
- and
- executing link synchronization operations based on the mismatch metric.
2 more elements
A system comprising:
- a first integrated circuit (IC) having a transmitter;
- a serial communication interface;
- and
- a second IC having a receiver, the receiver configured to:
- receive a set of data bits;
- compare each bit of a set of data bits to a respective bit of a sync pattern to detect a corresponding bit mismatch;
- determine a mismatch metric based on the corresponding bit mismatch and an adjustable scaling factor;
- and
- execute link synchronization operations based on the mismatch metric.
6 more elements
Dependencies are inferred from the claim text.