Self-Synchronized Scheme For Enforcing Phase Coherency In A System With Multiple Frequency Dividers

A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers comprising:

• synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases comprising a common phase;
• and
• applying the global reset to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase,
• wherein applying the global reset enables respective state transitions by deactivating a respective voltage clamp on the second output and the third output.

An apparatus comprising:

• a Voltage Controlled Oscillator (VCO);
• a first divider electrically coupled to the VCO and configured to generate a first output comprising a first state transition by dividing a VCO output of the VCO, the VCO output comprising a plurality of phases comprising a common phase;
• a synchronizer configured to synchronize an asynchronous reset to the first output to generate a global reset, a second divider electrically coupled to the VCO and configured to generate a second output comprising a second state transition during the common phase in response to the global reset;
• and
• a third divider electrically coupled to the VCO and configured to generate a third output comprising a third state transition during the common phase in response to the global reset;
• and
• a regenerative circuit connected between the asynchronous reset and the global reset to reduce a metastable condition of the global reset during synchronizing of the asynchronous reset with the first output.

An apparatus comprising:

• a Voltage Controlled Oscillator (VCO);
• a first divider electrically coupled to the VCO and configured to generate a first output comprising a first state transition by dividing a VCO output of the VCO, the VCO output comprising a plurality of phases comprising a common phase;
• a synchronizer configured to synchronize an asynchronous reset to the first output to generate a global reset, a second divider electrically coupled to the VCO and configured to generate a second output comprising a second state transition during the common phase in response to the global reset;
• and
• a third divider electrically coupled to the VCO and configured to generate a third output comprising a third state transition during the common phase in response to the global reset,
• wherein the global reset is connected to a respective voltage clamp of the second divider and the third divider, wherein each respective voltage clamp is configured to enable a respective state transition on the second output and the third output beginning during the common phase.