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US 2026/0113009 A1Published application
Analog processing of signed weights in activation functions
AssigneeMicron Technology, Inc.
InventorMichele Piccardi
Life of this patent
Estimating the term…
Abstract
Memories might include a controller configured to cause the memory to sample a first current level from a common source to a first input of a transimpedance amplifier (TIA) during a first sensing operation, e.g., of memory cells storing first signed weights, sample a second current level from the common source to the first input of the TIA during a second sensing operation, e.g., of memory cells storing second signed weights, isolate the common source from the first input of the TIA, and supply the sampled first current level to the first input of the TIA and sink the sampled second current level from the first input of the TIA.
Claims20
A memory, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a common source selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a transimpedance amplifier (TIA) having a first input selectively connected to the common source, a second input configured to receive a reference voltage level, an output, an impedance connected between the first input and the output, and a switch connected between the first input and the output in parallel with the impedance;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- perform a first sensing operation on a first plurality of selected memory cells of the plurality of strings of series-connected memory cells while the common source is connected to the first plurality of selected memory cells and to the first input of the TIA, and while the switch is closed;
- sample a first current level from the common source to the first input of the TIA;
- perform a second sensing operation on a second plurality of selected memory cells of the plurality of strings of series-connected memory cells while the common source is connected to the second plurality of selected memory cells and to the first input of the TIA, and while the switch is closed;
- sample a second current level from the common source to the first input of the TIA;
- isolate the common source from the first input of the TIA;
- and
- supply the sampled first current level to the first input of the TIA and sink the sampled second current level from the first input of the TIA while the switch is open to develop an output voltage level on the output of the TIA.
10 more elements
A memory, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a common source selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- and
- a transimpedance amplifier (TIA), comprising:
- a first input selectively connected to the common source;
- a second input configured to receive a reference voltage level;
- an output;
- an impedance connected between the first input and the output;
- a first switch connected between the first input and the output in parallel with the impedance;
- a first n-type field-effect transistor (nFET) having a first source/drain connected to a first voltage node configured to receive a first voltage level, having a second source/drain connected to the first input of the TIA through a second switch, and having a control gate;
- a second nFET having a first source/drain connected to a second voltage node configured to receive the first voltage level, having a second source/drain connected to the output, and having a control gate selectively connected to the control gate of the first nFET through a third switch;
- a third nFET having a control gate selectively connected to the control gate of the second nFET through a fourth switch, having a first source/drain connected to a third voltage node configured to receive the first voltage level, and having a second source/drain;
- a first p-type field-effect transistor (pFET) having a first source/drain connected to a fourth voltage node configured to receive a second voltage level higher than the first voltage level, having a second source/drain selectively connected to the first input of the TIA through a fifth switch, and having a control gate;
- a second pFET having a first source/drain connected to a fifth voltage node configured to receive the second voltage level, having a second source/drain connected to the second source/drain of the third nFET, and having a control gate connected to its second source/drain and selectively connected to the control gate of the first pFET through a sixth switch;
- a first capacitance having a first electrode connected to the control gate of the first pFET, and a second electrode connected to a sixth voltage node configured to receive a reference potential;
- and
- a second capacitance having a first electrode connected to the control gate of the first nFET, and a second electrode connected to a seventh voltage node configured to receive the reference potential.
15 more elements
A memory, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a common source selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a transimpedance amplifier (TIA) having a first input selectively connected to the common source, a second input configured to receive a reference voltage level, an output, and an impedance connected between the first input and the output, wherein the first input is further selectively directly connected to the output bypassing the impedance;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- apply a sense voltage level to an access line connected to a first plurality of selected memory cells of the plurality of strings of series-connected memory cells during a first sensing operation, wherein the sense voltage level is configured to activate a selected memory cell having a first data state and to deactivate a selected memory cell having a second data state;
- apply a second voltage level to each data line of the plurality of data lines that is connected to a selected memory cell of the first plurality of selected memory cells, wherein the second voltage level is indicative of a value of a digit of an input vector;
- connect the first input of a transimpedance amplifier (TIA) to the common source, isolate the first input of the TIA from a first pFET and a first nFET, and directly connect the first input of the TIA to the output of the TIA;
- connect a control gate of a second nFET to a control gate of a third nFET, wherein the second nFET is configured to sink a current level from the TIA equal to a first current level received from the common source during the first sensing operation;
- connect a control gate of the first pFET to a control gate of a second pFET connected to the third nFET while the first pFET is isolated from the first input of the TIA, wherein the second pFET is a diode-connected pFET;
- isolate the control gate of the first pFET from the control gate of the second pFET;
- apply the sense voltage level to an access line connected to a second plurality of selected memory cells of the plurality of strings of series-connected memory cells during a second sensing operation;
- apply the second voltage level to each data line of the plurality of data lines that is connected to a selected memory cell of the second plurality of selected memory cells;
- connect the first input of the TIA to the common source, isolate the first input of the TIA from the first pFET and the first nFET, and directly connect the first input of the TIA to the output of the TIA;
- connect the control gate of the first nFET to the control gate of the second nFET;
- isolate the control gate of the first nFET from the control gate of the second nFET, then isolate the first input of the TIA from the common source;
- and
- concurrently connect the first pFET and the first nFET to the first input of the TIA while the first input of the TIA is connected to the output of the TIA through the impedance of the TIA without the direct connection.
16 more elements
Dependencies are inferred from the claim text.