Nonvolatile memory device supporting gidl erase operation

A memory device comprising:

• a memory cell array including a plurality of memory blocks;
• a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, the target block being a block in which an erase operation is to be performed;
• and
• control logic configured to control the memory cell array and the voltage generator,
• wherein the voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and
• the control logic is configured to change at least one of a slope of the erase voltage or a floating time of at least one row line among the row lines, the change in the slope or in the floating time being dependent on a number of executed program/erase cycles, wherein,
• in response to the number of executed program/erase cycles of the target block being equal to a count, the control logic is configured to decrease the slope of the erase voltage.