Memory performing reset operation and operating method thereof

A memory comprising:

• a cell string including memory cells connected between a bit line and a source line;
• select lines for controlling a connection between the bit line and the cell string and a connection between the source line and the cell string;
• word lines for controlling the memory cells;
• a watchdog circuit detecting a failing of a reset operation as a fail;
• and
• a reset control circuit for generating discharge control signals in response to the detection of the fail by the watchdog circuit, wherein the discharge control signals cause at least a part of the word lines, the select lines, and the bit line to be discharged, and wherein the reset control circuit is further for activating a reset signal after at least a part of the word lines, the select lines, and the bit line have been discharged.