Nonvolatile memory device and memory package including the same

A nonvolatile memory device comprising:

• a first semiconductor layer including:
• a plurality of wordlines extending in a first direction;
• a plurality of bitlines extending in a second direction crossing the first direction;
• and
• a memory cell array connected to the plurality of wordlines and the plurality of bitlines, the memory cell array including at least one memory block;
• and
• a second semiconductor layer beneath the first semiconductor layer in a third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including:
• a substrate;
• and
• an address decoder on the substrate, the address decoder configured to control the memory cell array,
• wherein the address decoder includes:
• a plurality of pass transistors connected to the plurality of wordlines;
• and
• a plurality of drivers configured to control switching operations of the plurality of pass transistors,
• wherein a first memory block of the at least one memory block includes a first cell region including a plurality of memory cells, and a first extension region adjacent to a first side of the first cell region,
• wherein the second semiconductor layer includes a first region and a second region that is spaced apart from the first region in at least one of the first direction and the second direction, the first region comprising the plurality of pass transistors and the second region comprising the plurality of drivers,
• wherein first pass transistors connected to first wordlines connected to the first memory block are disposed in the first region of the second semiconductor layer, at least part of the first region overlapped the first extension region in a plan view, and
• wherein a first length for first side of the first region in the second direction is different from a second length for second side of the second region in the second direction.

A memory package comprising:

• a base substrate;
• and
• a plurality of memory chips stacked on the base substrate,
• wherein each of the plurality of memory chips includes:
• a first semiconductor layer including:
• a plurality of wordlines extending in a first direction;
• a plurality of bitlines extending in a second direction crossing the first direction;
• and
• a memory cell array connected to the plurality of wordlines and the plurality of bitlines, the memory cell array including at least one memory block;
• and
• wherein each of the plurality of memory chips further includes:
• a second semiconductor layer beneath the first semiconductor layer in a third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including:
• a substrate;
• and
• an address decoder on the substrate, the address decoder configured to control the memory cell array,
• wherein the address decoder includes:
• a plurality of pass transistors connected to the plurality of wordlines;
• and
• a plurality of drivers configured to control switching operations of the plurality of pass transistors,
• wherein a first memory block of the at least one memory block includes a first cell region including a plurality of memory cells, and a first extension region adjacent to a first side of the first cell region,
• wherein the second semiconductor layer includes a first region and a second region that is spaced apart from the first region in at least one of the first direction and the second direction, the first region comprising the plurality of pass transistors and the second region comprising the plurality of drivers,
• wherein first pass transistors connected to first wordlines connected to the first memory block are disposed in the first region of the second semiconductor layer, at least part of the first region overlapped the first extension region in a plan view, and
• wherein a first length for first side of the first region in the second direction is different from a second length for second side of the second region in the second direction.

A nonvolatile memory device comprising:

• a first semiconductor layer including:
• a plurality of wordlines extending in a first direction;
• a plurality of bitlines extending in a second direction crossing the first direction;
• and
• a memory cell array connected to the plurality of wordlines and the plurality of bitlines, the memory cell array including at least one memory block;
• and
• a second semiconductor layer beneath the first semiconductor layer in a third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including:
• a substrate;
• and
• an address decoder on the substrate, the address decoder configured to control the memory cell array,
• wherein the address decoder includes:
• a plurality of pass transistors connected to the plurality of wordlines;
• and
• a plurality of drivers configured to control switching operations of the plurality of pass transistors,
• wherein a first memory block of the at least one memory block includes a first cell region including a plurality of memory cells, a first extension region adjacent to a first side of the first cell region, and a second extension region adjacent to a second side of the first cell region opposite the first side of the first cell region,
• wherein the second semiconductor layer includes a first region, a second region and a third region that are spaced apart from each other in at least one of the first direction and the second direction, the first region comprising first pass transistors connected to first wordlines connected to the first memory block, the second region comprising second pass transistors connected to the first wordlines, the third region comprising the plurality of drivers,
• wherein the first pass transistors are disposed in the first region of the second semiconductor layer and the second pass transistors are disposed in the second region of the second semiconductor layer, at least part of the first region overlapped the first extension region in a plan view and at least part of the second region overlapped the second extension region in the plan view,
• wherein a first length for first side of the first region is different from a second length for second side of the third region in the second direction, and a third length for third side of the second region is different from the second length for the second side of the third region in the second direction, and
• wherein the first semiconductor layer further includes a plurality of first metal pads, the second semiconductor layer further includes a plurality of second metal pads, and the plurality of first metal pads and the plurality of second metal pads are connected by a bonding method.