Flexible logic unit adapted for real-time task switching

An arrangement, comprising (A) a matrix with (a) a plurality of programmable logic units and (b) a plurality of first one bit clocked storage elements, the programmable logic units and first one bit clocked storage elements being arranged in an array, the arrangement being adapted for sequential execution of at least two tasks;

• and
• (B) a configuration bit memory whereby for each of the programmable logic unit(s), a configuration bit storage circuit is provided to store a configuration bit from the memory.

An arrangement adapted for low power consumption, the arrangement comprising (A) a matrix with (i) a plurality of programmable logic units and (ii) a plurality of first one bit clocked storage elements, the programmable logic units and first one bit clocked storage elements being arranged in an array, the arrangement being adapted for sequential execution of at least two tasks, whereby for each of the first one bit clocked storage elements a data store and restore circuit is provided for local storing or restoring the respective values per task of the first one bit clocked storage elements, and

• (B) a data memory, external to the matrix, wherein the data store and restore circuit is provided for (i) pre-loading data related to one task from the memory into the data and restore circuit and/or (ii) post-storing of data related to one task in the data store and restore circuit to the data memory, whereby the pre-loading and/or post-storing can be performed while either when another task is executed without disturbing the task execution or when the matrix is inactive to save power consumption.

An arrangement, adapted for a safe execution of tasks, the arrangement comprising (A) a matrix with (i) a plurality of programmable logic units and (ii) a plurality of first one bit clocked storage elements,

• the programmable logic units and first one bit clocked storage elements being arranged in an array, the arrangement being adapted for sequential execution of at least two tasks, whereby for each of the first one bit clocked storage elements a data store and restore circuit is provided for local storing or restoring the respective values per task of the first one bit clocked storage elements, wherein the two tasks are the same, such that the same algorithm with exact same temporal execution is executed and the safeness of the execution is verified by comparing the outputs of the tasks.