Clock signal correction device and semiconductor device including the same

A semiconductor device, comprising:

• a memory controller configured to output, in a first mode, a first clock signal of a first frequency and output, in a second mode different from the first mode, a mode signal indicative of the second mode;
• and
• a memory device configured to
• generate, using the first clock signal in the first mode, a plurality of first multi-phase clock signals having different phases,
• generate, based on the mode signal, a second clock signal of a second frequency,
• generate a third clock signal based on a plurality of second multi-phase clock signals that have different phases, the plurality of second multi-phase clock signals being generated using the second clock signal, and
• determine, based on a duty cycle of the third clock signal, a value of a skew code for adjusting phases of the plurality of first multi-phase clock signals.

A computing system comprising:

• a memory controller configured to transmit a data clock signal and data based on a host request and transmit a mode signal indicating that a computing system has entered a first mode;
• and
• a memory device configured to:
• generate a clock signal based on the mode signal,
• generate a monitoring clock signal having a logic state that transitions in synchronization with edges of clock signals of a plurality of internal clock signals, the plurality of internal clock signals having different phases and being generated based on the clock signal, and the monitoring clock signal having a plurality of waveforms corresponding to a plurality of codes, the plurality of codes configured to adjust at least one duty cycle of the clock signals of the plurality of internal clock signals,
• generate, using the data clock signal, a plurality of multi-phase clock signals having different phases, and
• adjust phases of the plurality of multi-phase clock signals using the code that is determined based on a duty ratio of the monitoring clock signal.